4 Parallel Prefix Adder

VLSI Integer adders find applications in Arithmetic and Logic Units (ALUs), microprocessors and memory addressing units. Speed of the adder often decides the minimum clock cycle time in a microprocessor. The need for a Parallel Prefix Adder (PPA) is that it is primarily fast when compared with a ripple carry adder. PPA is a family of adders derived from the commonly known carry look ahead adders. These adders are suited for additions with wider word lengths. PPA circuits use a tree network to reduce the latency to 2 (log ) O n where ‘n’ represents the number of bits. This chapter deals with the design proposal and implementation of new prefix adder architecture for 8-bit, 16-bit, 32-bit and 64-bit addition. The proposed architectures have the least number of computation nodes when compared with existing one’s. This reduction in hardware of the proposed architectures helps to reap a benefit in the form of reduced power and power-delay product. The proposed architectures are realized using three schemes namely Scheme I, Scheme II and Scheme III. Scheme III Consumes least power when compared to Scheme I and Scheme II. Scheme I performs computation at a faster rate when compared with other schemes.